ToughSwitch™ PRO vs WISP Switch™ Packet Buffers

[sirhc]

This is the specs for the BCM53118 switch core used in the Ubiquiti® ToughSwitch™ PRO.
This switch core was designed for small home office networks acording to Broadcom® category the switch core is listed in.

Below I made the text green for features Ubiquiti® implimented and red for those not implemented.
Note that some red items could indeed be implemented just not configurable.

Black or normal text for just informational.

• Highly integrated, non-blocking 9-port 10/100/1000 switch silicon that integrates:
• Eight 10/100/1000 PHYs
• One GMII/RGMII interface for an Inband Management Port (IMP) for glueless connection to a CPU/management entity
• Serial EEPROM, MDC/MDIO, SPI, and Interrupt-to-CPU interfaces
• Broadcom’s LoopDTech™ and CableChecker™ help reduce network downtime and minimize installation, maintenance, and support efforts
• LoopDTech technology provides loop detection without running spanning tree protocol
• CableChecker enables advanced cable diagnostics based on the Broadcom® Convergence Algorithm
• Virtual Local-Area Network (VLAN)
• IEEE 802.1Q-based VLAN with 4K entries
• Port-based VLAN
• VLAN double tagging (Q-in-Q)
• Quality of Service (QoS)
• Four selectable QoS per port; SP and WRR
• Port, MAC, IEEE 802.1P, and IPv4/IPv6 DSCP based QoS
• Performance
• 9 KB jumbo frame support; wirespeed performance for all fame sizes
• 4K MAC addresses with automatic learning and aging
• 256 multicast group support
• 196-KB packet buffer
• Security
• IEEE 802.1x support for secure user authentication
• DoS prevention hardware
• Traffic control and network resiliency
• Storm control and port-based ingress/egress rate control
• Spanning Tree support (Rapid Spanning Tree and Multiple Spanning Trees—up to 16)
• IPv4 IGMP and IPv6 MLD snooping
• IEEE 802.3x programmable per-port flow control and backpressure
• Port mirroring, LLDP, LACP
• Management
• On-chip MIB counters to collect receive and transmit statistics for each port, hardware support for SNMP/MIBs and RMON
• Technology and physical specifications
• State-of-the-art 65 nm LP, 6-layer metal technology
• 1.2V core and 3.3V I/O
• Typical power consumption less than 3.9W

53118.png (32.23 KiB) Viewed 95174 times

You might notice that there is only 192KB of memory for packet buffers which is on the low side for a commercial switch for towers.
Ubiquiti® used the Atheros® AR7240 SOC for it's MIPS24K 400MHz CPU to drive the UI and perform switch core configuration and run SNMP, ping watchdog and other trivial utilities.

The speed of the CPU has no influence on the switch performance as the switch core handles all of that on it's own once configured.

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Below is the specs for the Vitesse® VSC7427 SOC / Switch core we used for our WISP Switch product line.
This switch core was designed for Eenterprise networks acording to Vitesse catagory this switch core is listed in.

Below I made the text green for features Netonix(R) implemented, blue for feature we may implement, and red for those not implemented.

Black or normal text for just informational.
• Lowest power 26-port Gigabit Ethernet switch available in the market
• Green energy efficiency modes including ActiPHY™, PerfectReach™, and Draft IEEE 802.3az
• Two ICs reduce overall power requirements
• Optimal power consumption for all link speeds Features
• Twelve integrated IEEE 802.3ab-compliant 10/100/1000BASE-T Ethernet copper transceivers with VeriPHY™ cable diagnostics
• Three QSGMII MAC interfaces
• Integrated 416 MHz MIPS CPU with DDR2 and serial Flash interface
• Advanced Access and QoS Control Lists (ACL and QCL) support through TCAM-based match patterns
• Integrated temperature monitoring circuit
• Integrated fan controller - ENHANCED BY NETONIX®
• 8 K MAC addresses and 4 K VLAN support
• Supports IEEE 1149.1 JTAG boundary scan, IEEE 1149.6 AC-JTAG, QSGMII v1.2, 1 Gbps SGMII, and 100BASE-FX and 1000BASE-X Layer 2 Switching
• 26-port Gigabit Ethernet switch with nonblocking wire-speed performance
• Link aggregation (IEEE 802.3ad) with programmable traffic distribution based on Layer 2 through Layer 4 information
• Wire-speed hardware-based learning and CPU-based learning configurable per port
• Independent and shared VLAN learning
• Spanning Tree support, Rapid Spanning Tree, and Multiple Spanning Tree
• IEEE 802.3x programmable per-port flow control and backpressure
• Jumbo frame support up to 12.2 kilobytes with per-port programmable MTU
• Q-in-Q tagging support
• 4 megabits of integrated shared packet memory
• Audio and video bridging (AVB) QoS
• Eight QoS queues per port with strict or deficit-weighted round robin scheduling
• QoS classification based on IEEE 802.1p, EtherType, VID, MAC/IP addresses, IPv4/IPv6 DSCP, and UDP/TCP ports and ranges
• Data rate shaper and policer per-queue, per-port for both ingress and egress directions
• Full-duplex flow control (IEEE 802.3x) and half-duplex backpressure, symmetric and asymmetric
• Multicast and broadcast storm control with flooding control

WS-24-400B.png (158.79 KiB) Viewed 95174 times

This is not all the specs but a quick look.
The important thing here is the WISP Switch™ has 4Mb of packet buffer memory verses the ToughSwitch™ 192K.
I hope this was informative and may answer some questions I have seen over on the UBNT Forum about packet buffer memory but that I am unable to answer there.

[wisphopefull]

Great info, don't you mean 4 megabytes rather than bits of buffer memory?

Also, how much buffer memory will the TowerSwitch have?
TowerSwitch would be more comparable to the ToughSwitch for tower sites.

[sirhc]

Great info, don't you mean 4 megabytes rather than bits of buffer memory?

Also, how much buffer memory will the TowerSwitch have?
TowerSwitch would be more comparable to the ToughSwitch for tower sites.

No, it is 4Mb which is a TON more then 192K.

Even though the TS is 8 port if you divide 192K by 8 ports you only have 24K per port.
The TS5 only has 128K of packet buffer memory.

If you divide 4,096K by 24 you have 170K per port (almost 7 times more) but it is a shared pool so 4Mb is a lot!

Plus it also comes down to how the switch core handles packets with Flow Control.

With our switch you turn on or off flow control per port.

Even the Vitesse VSC7429 Switch Core which is a true carrier class switch core still only has 4Mb of packet buffer for a 24+2 port switch.
We can drop the VSC7429 SOC into our switches but our tests indicate the VSC7427 is more then enough for WISP tower switches.
We beat the crap out of them at my WISP and you all know my WISP offers very fast program speeds.

I know I keep telling you guys 2 weeks and it is getting old but in tis business if you change one little thing it throws you back 2 to 4 weeks.

I can tell you you will start seeing them soon!

[sirhc]

Also, how much buffer memory will the TowerSwitch have?
TowerSwitch would be more comparable to the ToughSwitch for tower sites

Same packet buffer memory, 4Mb is a lot for a switch.
Actually the WISP Switch is more like the ToughSwitch just a much better design in my opinion, it is meant to be mounted in ground box.

The TOWER Switch is a SPLIT design. The switch board is in an outdoor box of it's own meant to mount on the tower where your radios are. Then there is a 19" rack mountable box at the bottom of the tower which has some electronics in it (TOP SECRET) with the power supply. Then there is a fiber copper composite cable that connects the two together.

The distance between the boxes can be much longer than the normal 100 meter Ethernet limit currently and for those on AM/FM broadcast towers it will eliminate Ethernet interference issues.

I will be annoucing specs and pictures in October or MAYBE sooner, my current goal is to get WISP Switch and CAP-FXS on the market.

[Sp1]

Any chance you will be adding • Q-in-Q tagging support this would help with our DR/business continuity offerings as well as multi site business networks.

[sirhc]

Any chance you will be adding • Q-in-Q tagging support this would help with our DR/business continuity offerings as well as multi site business networks.

THis is slated for v1.2.0 firmware, not sure when but it is on the road map, probably before Spring.

[mike99]

You could remove STP / RSTP (or change for a color that indicate broken) for thoughswitch since it's broken (STP work only with untagged VLAN but only use tagged VLAN and it won't be to detect loop and will become unresponsive) and Ubnt don't seem to want to fix it. I've been writing to them about this since january and the don't even answer anymore.

[Ludvik]

No, it is 4Mb which is a TON more then 192K.

Even though the TS is 8 port if you divide 192K by 8 ports you only have 24K per port.
The TS5 only has 128K of packet buffer memory.

BCM53118 have 196KB buffer. It is 1.5 Mb.

Smaller than vitesse, yes. But huge difference?

[sirhc]

No, it is 4Mb which is a TON more then 192K.

Even though the TS is 8 port if you divide 192K by 8 ports you only have 24K per port.
The TS5 only has 128K of packet buffer memory.

BCM53118 have 196KB buffer. It is 1.5 Mb.

Smaller than vitesse, yes. But huge difference?

According to their Data Sheet 196KB is correct: https://www.broadcom.com/collateral/pb/53118-PB00-R.pdf

[mike99]

192 KB = 1.5 Mb (192*8=1536)